In the field of testing (e.g. when testing a chip, or a loaded printed, circuit board) signals from different test pins (e.g. pins or test points of a chip, or nodes of a loaded printed circuit board) are captured using a plurality of individual channels. For example, a device under test having a plurality of test pins (input pins, output pins, input/output pins, test points or circuit nodes) is connected to a plurality of test channels. Each test channel receives information of one test pin. Moreover, each channel typically performs a processing of the data captured by the respective channel.
In the following, a conventional test system will be described with reference to FIG. 10. For this purpose, FIG. 10 shows a block schematic diagram of a test system. The test system of FIG. 10 is designated in its entirety with 1000. The test system 1000 comprises a device under test 1010 and, for example, an n+1 digital channels 1020_0-1020_n. The device under test further comprises n+1 terminals or test pins 1030_0-1030_n. Each of the test channels 1020_0-1020_n comprises a digital frontend 1040_0-1040_n, a test processor 1044_0-1044_n and a memory 1048_0-1048_n. In the following, the structure of the digital channel 1020_0 for bit0 will be described.
A connection of the digital frontend 1040_0 is coupled with test pin 1030_0 of the device under test 1010 for bit0. Moreover, the digital frontend 10400 is coupled with the test processor 1044_0. For example, the test processor 1044_0 can output a signal 10460 to the test pin 1030_0 via the digital frontend 1040_0. Moreover, the test processor 1044_0 may be adapted to receive a signal from the test pin 1030_0 via the digital frontend 1040_0. Thus, the digital frontend 1040_0 constitutes an interface between the test processor 1044_0 and the test pin 1030_0 of the device under test. Moreover, the test processor 1044_0 is coupled to a corresponding memory 1048_0.
Thus, the digital channel 1020_0 is, for example, adapted to receive a digital (or analog) pattern present at the test pin 1030_0 for bit0 and to store the pattern present at the test pin 1030_0 in the memory 1048_0. Similarly, the n-th digital channel 1020_n may be adapted to receive an analog or digital pattern present at the n-th test pin 1030_ of the device under test and to store the respective pattern in the memory 1048_n. However, it should be noted that the parallel PUT output data of the device under test 1010 are captured per pin. In other words, each digital channel 1020_0-1020_n comprises or contains) the data of a single bit. In other words, each of the digital channels 1020_0-1020_n has access to only one test pin 1030_0-1030_n of the device under test 1010.
Consequently, a parallel capture of the output data of the device under test 1010 leads to a pattern of distributed data in the memories 1048_0-1048_n of the digital channels 1020_0-1020_n.
In general, it can be stated that the parallel capture of output data from devices under test leads to distributed data in automated test equipment (ATE) systems.
Further, it should be noted that in many tests (e.g. analog-to-digital converter testing, parallel protocol test) the complete data is necessary to compute test results. However, in a conventional test system the data is distributed, between the channels, and the test processor of each channel has no access to the memory of different channels. Therefore, a single test processor is not able to compute results.
To achieve best cost of test, an automated test equipment (ATE) system shall test devices under test as fast as possible. Making use of conventional concepts, having distributed data leads to increased test times. Distributed data is conventionally uploaded from the test system into a workstation, where it is combined and processed. It should be noted here that starting an upload typically brings along a latency, wherein this latency typically occurs per channel. In the case of multi-site testing (e.g. when testing several devices under test at the same time) computing of the results out of the captured data is typically serial for each site, as a workstation is not able to do parallel processing (at least not in an efficient way).
Moreover, in the case that several algorithms have to be applied to the capture data, the computation in the workstation is typically performed serially, as a workstation is typically not able to do parallel processing. Moreover, in the case that the capture data has to be applied as a stimulus for different tests, the combined data has to be downloaded to the test system again.